View DS3905_178750.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Rev 1; 8/03
Triple 128-Position Nonvolatile Digital Variable Resistor/Switch
General Description
The DS3904/DS3905 contain three nonvolatile (NV) low temperature coefficient, variable digital resistors. Each resistor has 128 user-selectable positions. Additionally, the DS3904/DS3905 have a high-impedance setting that allows each resistor to function as a digital switch. The DS3904/DS3905 can operate over a 2.7V to 5.5V supply voltage range, and communication with the device is achieved through a 2-wire serial interface. Address pins allow multiple DS3904/DS3905s to operate on the same two-wire bus. The DS3904 has one address pin, allowing two DS3904s to share the bus, while the DS3905 has three address pins, allowing up to eight DS3905s to share a common bus. The low-cost and small size of the DS3904/DS3905 make them ideal replacements for conventional mechanical trimming resistors.
Features
Three 20k, 128-Position Linear Digital Resistors Resistor Settings are Stored in NV Memory Each Resistor has a High-Impedance Setting for Switch Operation to Control Digital Logic Low Temperature Coefficient 2-Wire Serial Interface 2.7V to 5.5V Operating Range -40C to +85C Industrial Temperature Packaging: 8-Pin SOP for DS3904, 10-pin SOP for DS3905
DS3904/DS3905
Ordering Information
PART TEMP RANGE -40C to +85C -40C to +85C PINPACKAGE 8 SOP 10 SOP RESISTANCE 20k + Hi-Z 20k + Hi-Z
Applications
Power-Supply Calibration Cell Phones and PDAs Fibre Optic Transceiver Modules Portable Electronics Small and Low-Cost Replacement for Conventional Mechanical Trimming Resistors/ Dip Switches Test Equipment
DS3904U-020 DS3905U-020
Pin Configurations
TOP VEIW
SDA 1 SCL 2 VCC 3 GND 4
8 7
A0 H0 H1 H2
A1 1 SDA 2 SDL 3 VCC GND 4 5
10 A2 9 A0 H0 H1 H2
DS3904
6 5
DS3905
8 7 6
SOP
SOP
Typical Operating Circuit
INTERFACE EXAMPLES VCC VCC
DS3904/DS3905
0.1F 4.7k 2-WIRE MASTER 4.7k SCL SDA RESISTOR 1 20k ADDR F9h RHIZ H1 R11 DIGITAL LOGIC 2-WIRE ADDRESSABLE SWITCH (USING 00h AND RHIZ SETTINGS) VCC RESISTOR 0 20k ADDR F8h RHIZ H0 VCC R10 VARIABLE RESISTANCE FOR ADJUSTABLE CURRENT SOURCE
A0 (DS3905 ONLY) A1 A2
VIN RHIZ H2
RESISTOR 2 20k ADDR FAh GND
GAIN CONTROL
R12
_____________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Triple 128-Position Nonvolatile Variable Digital Resistor/Switch DS3904/DS3905
ABSOLUTE MAXIMUM RATINGS
Voltage on VCC Pin Relative to Ground.................-0.5V to +6.0V Voltage on SDA, SCL, A0, A1, A2 Relative to Ground*...................................-0.5V to VCC + 0.5V Voltage on H0, H1, and H2 Relative to Ground .......................................-0.5V to +6.0V Current Through H0, H1, and H2..........................................3mA *This voltage must not exceed 6.0V.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Operating Temperature Range ...........................-40C to +85C Programming Temperature Range .........................0C to +70C Storage Temperature Range .............................-55C to +125C Soldering Temperature ................See J-STD-020A Specification
RECOMMENDED DC OPERATING CONDITIONS
(TA = -40C to +85C)
PARAMETER Supply Voltage Input Logic 1 Input Logic 0 Resistor Current Resistor Terminals H0, H1, H2 SYMBOL VCC VIH VIL IR VCC = +2.7V to +5.5V -0.3 (Note 1) CONDITIONS MIN 2.7 0.7 x VCC -0.3 TYP MAX 5.5 VCC + 0.3 0.3 x VCC 3 +5.5 UNITS V V V mA V
DC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40C to +85C, unless otherwise noted.)
PARAMETER Input Leakage Standby Supply Current Low-Level Output Voltage (SDA) SYMBOL IL ISTBY VOL1 VOL2 CONDITIONS (Note 2) VCC = 3V (Note 3) VCC = 5V (Note 3) 3mA sink current 6mA sink current 0 0 MIN -1 TYP 95 145 MAX +1 200 200 0.4 0.6 UNITS A A V
ANALOG RESISTOR CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40C to +85C, unless otherwise noted.)
PARAMETER Absolute Linearity Relative Linearity Temperature Coefficient Position 7Fh Resistance Position 00h Resistance High Impedance RMAX RMIN RHI-Z SYMBOL (Note 4) (Note 5) Position 7Fh (Note 6) TA = +25C TA = +25C CONDITIONS MIN -1 -0.5 -200 14.5 200 5.5 +123 20 TYP MAX +1 +0.5 +400 25.5 500 UNITS LSB LSB ppm/C k M
2
______________________________________________________________________
Triple 128-Position Nonvolatile Digital Variable Resistor/Switch DS3904/DS3905
AC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40C to +85C.)
PARAMETER SCL Clock Frequency (Note 7) Bus Free Time between STOP and START Conditions (Note 7) Hold Time (Repeated) START Condition (Notes 7, 8) Low Period of SCL Clock (Note 7) High Period of SCL Clock (Note 7) Data Hold Time (Notes 7, 9) Data Setup Time (Note 7) Start Setup Time Rise Time of Both SDA and SCL Signals (Note 10) Fall Time of Both SDA and SCL Signals (Note 10) Setup Time for STOP Condition Capacitive Load for Each Bus Line EEPROM Write Time Startup Time SYMBOL fSCL tBUF tHD:STA tLOW tHIGH tHD:DAT tSU:DAT tSU:STA tR tF tSU:STO CB tW tST Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode (Note 10) (Note 11) 20 2 CONDITIONS MIN 0 0 1.3 4.7 0.6 4.0 1.3 4.7 0.6 4.0 0 0 100 250 0.6 4.7 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 0.6 4.0 400 300 1000 300 300 0.9 0.9 TYP MAX 400 100 UNITS kHz s s s s s ns s ns ns s pF ms ms
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = +70C.)
PARAMETER EEPROM Writes SYMBOL CONDITIONS MIN 50,000 TYP MAX UNITS
_____________________________________________________________________
3
Triple 128-Position Nonvolatile Digital Variable Resistor/Switch DS3904/DS3905
NONVOLATILE MEMORY CHARACTERISTICS (continued)
(VCC = +2.7V to +5.5V, TA = +70C.)
All voltages are referenced to ground. Applies to A0, SDA, SCL for the DS3904 and A0, A1, A2, SDA, SCL for the DS3905. Also applies to H0, H1, H2 for both DS3904 and DS3905 when in the high-impedance state. Note 3: ISTBY specified with SDA = SCL = VCC and A0 = GND. Note 4: Absolute linearity is used to determine expected resistance. Absolute linearity is defined as the deviation from the straight line drawn from the value of the resistance at position 00h to the value of the resistance at position 7Fh. Note 5: Relative linearity is used to determine the change of resistance between two adjacent resistor positions. Note 6: Temperature coefficient specifies the change in resistance as a function of temperature. The temperature coefficient varies with resistor position. Limits are guaranteed by design. Note 7: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000ns + 250ns =1250ns before the SCL line is released. Note 8: After this period, the first clock pulse is generated. Note 9: The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. Note 10: CB--total capacitance of one bus line in picofarads, timing referenced to 0.9 x VCC and 0.1 x VCC. Note 11: EEPROM write begins after a stop condition occurs.
Note 1: Note 2:
4
______________________________________________________________________
Triple 128-Position Nonvolatile Digital Variable Resistor/Switch
Typical Operating Characteristics
(VCC = +5.0V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
DS3904/5 toc01
DS3904/DS3905
SUPPLY CURRENT vs. SCL FREQUENCY
DS3904/5 toc02
RESISTANCE vs. RESISTOR SETTING
RESISTORS 0, 1, AND 2 20 RESISTANCE (k)
DS3904/5 toc03
160 140 SUPPLY CURRENT (A) 120 100 80 60 40 20 0 -40 -20 0 20 40 60 SDA = SCL =VCC ADDRESS PINS CONNECTED TO GND VCC = +5V VCC = +3V
200 180 160 SUPPLY CURRENT (A) 140 120 100 80 60 40 20 0 VCC = SDA = +5V ADDRESS PINS CONNECTED TO GND
25
15
10
5
0 0 50 100 150 200 250 300 350 400 SCL FREQUENCY (kHz) 0 25 50 75 100 125 RESISTOR SETTING (DEC)
80
TEMPERATURE (C)
TEMPERATURE COEFFICIENT vs. RESISTOR SETTING
DS3904/5 toc04
POSITION 7Fh RESISTANCE PERCENT CHANGE FROM +25C vs. TEMPERATURE
DS3904/5 toc05
POSITION 00h RESISTANCE PERCENT CHANGE FROM +25C vs. TEMPERATURE
RESISTANCE % CHANGE (FROM 25C) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5
DS3904/5 toc06
600 TEMPERATURE COEFFICIENT (ppm/C) 500 400 300 200 100 0 -100 0 20 40 60 80 100 120 RESISTOR SETTING (DEC) TC OF +25C TO +85C TC OF +25C TO -40C RESISTORS 0, 1, AND 2
1.0 RESISTANCE % CHANGE (FROM 25C) 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -40 -20 0 20 40 60 80 TEMPERATURE (C) RESISTORS 0, 1, AND 2
RESISTORS 0, 1, AND 2
-40
-20
0
20
40
60
80
TEMPERATURE (C)
RESISTANCE vs. POWER-UP VOLTAGE
DS3904/5 toc07
RESISTANCE vs. POWER-DOWN VOLTAGE
90 80 RESISTANCE (k) 70 60 50 40 30 20 10 0 6 0 1 2 3 4 PROGRAMMED RESISTANCE POSITION 3Fh 10.0 5 6 2.5 >5.5M RESISTORS 0, 1, AND 2
DS3904/5 toc08
POSITION 3Fh RESISTANCE vs. SUPPLY VOLTAGE
DS3904/5 toc09
100 90 80 RESISTANCE (k) 70 60 50 40 30 20 10 0 0
>5.5M
100
13.0 POSITION 3Fh RESISTANCE (k) 12.5 12.0 11.5 11.0 10.5 RESISTORS 0, 1, AND 2
RESISTORS 0, 1, AND 2 EEPROM RECALL
PROGRAMMED RESISTANCE POSITION 3Fh 1 2 3 4 5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
POWER-UP VOLTAGE (V)
POWER-DOWN VOLTAGE (V)
SUPPLY VOLTAGE (V)
_____________________________________________________________________
5
Triple 128-Position Nonvolatile Digital Variable Resistor/Switch DS3904/DS3905
Typical Operating Characteristics (continued)
(VCC = +5.0V, TA = +25C, unless otherwise noted.)
ABSOLUTE LINEARITY vs. RESISTOR 0 POSITION
DS3904/5 toc10
RELATIVE LINEARITY vs. RESISTOR 0 POSITION
DS3904/5 toc11
ABSOLUTE LINEARITY vs. RESISTOR 1 POSITION
RESISTOR 1 20k ABSOLUTE LINEARITY (LSB) 0.08
DS3904/5 toc12
0.10 RESISTOR 0 20k ABSOLUTE LINEARITY (LSB) 0.08
0.10 RESISTOR 0 20k RELATIVE LINEARITY (LSB) 0.08
0.10
0.06
0.06
0.06
0.04
0.04
0.04
0.02
0.02
0.02
0 0 20 40 60 80 100 120 RESISTOR 0 POSITION (DEC)
0 0 20 40 60 80 100 120 RESISTOR 0 POSITION (DEC)
0 0 20 40 60 80 100 120 RESISTOR 1 POSITION (DEC)
RELATIVE LINEARITY vs. RESISTOR 1 POSITION
DS3904/5 toc13
ABSOLUTE LINEARITY vs. RESISTOR 2 POSITION
DS3904/5 toc14
RELATIVE LINEARITY vs. RESISTOR 2 POSITION
RESISTOR 2 20k 0.08 RELATIVE LINEARITY (LSB)
DS3904/5 toc15
0.10 RESISTOR 1 20k RELATIVE LINEARITY (LSB) 0.08
0.10 RESISTOR 2 20k ABSOLUTE LINEARITY (LSB) 0.08
0.10
0.06
0.06
0.06
0.04
0.04
0.04
0.02
0.02
0.02
0 0 20 40 60 80 100 120 RESISTOR 1 POSITION (DEC)
0 0 20 40 60 80 100 120 RESISTOR 2 POSITION (DEC)
0 0 20 40 60 80 100 120 RESISTOR 2 POSITION (DEC)
6
______________________________________________________________________
Triple 128-Position Nonvolatile Digital Variable Resistor/Switch
Pin Description
NAME SDA SCL VCC GND H2 H1 H0 A0 A1 A2 PIN DS3904 DS3905 1 2 3 4 5 6 7 8 -- -- 2 3 4 5 6 7 8 9 1 10 DESCRIPTION 2-Wire Serial Data. Open-drain input/output for 2-wire data. 2-Wire Serial Clock. Input for 2-wire clock. Supply Voltage Terminal Ground Terminal Resistor 2 High Terminals Resistor 1 High Terminals Resistor 0 High Terminals Address-Select Pin Address-Select Pin (DS3905 Only) Address-Select Pin (DS3905 Only) FAh Resistor 2
DS3904/DS3905
Table 1. Variable Resistor Registers
ADDRESS F8h F9h VARIABLE RESISTOR Resistor 0 Resistor 1 POSITION 7Fh RESISTANCE 20k (nominal) 20k (nominal) 20k (nominal) NUMBER OF POSITIONS* 128 (00h to 7Fh) + Hi-Z 128 (00h to 7Fh) + Hi-Z 128 (00h to 7Fh) + Hi-Z
*Writing a value greater than 7Fh to any of the resistor registers sets the high-impedance mode control bit (RHIZ, the MSB of the resistor register) resulting in the resistor going into highimpedance mode. Position 0 is the minimum position. Position 127 is the maximum position.
Device Operation Detailed Description
The DS3904/DS3905 contain three, 128-position, NV, low temperature coefficient, variable digital resistors. They are controlled through a 2-wire serial interface, and can serve as a low-cost replacement for designs using conventional trimming resistors. Furthermore, the DS3904 address pin (A0) allows two DS3904s to be placed on the same 2-wire bus. The three address pins on the DS3905 allow up to eight DS3905s to be placed on the same 2-wire bus. With their low cost and small size, the DS3904/DS3905 are well tailored to replace larger mechanical trimming variable resistors. This allows the automation of calibration in many instances because the 2-wire interface can easily be adjusted by test/production equipment.
Clock and Data Transitions
The SDA pin is normally pulled high with an external resistor or device. Data on the SDA pin can only change during SCL low time periods. Data changes during SCL high periods indicate a start or stop condition depending on the conditions discussed below. See the timing diagrams for further details (Figures 2 and 3).
Start Condition
A high-to-low transition of SDA with SCL high is a start condition, which must precede any other command. See the timing diagrams for further details (Figures 2 and 3).
Stop Condition
A low-to-high transition of SDA with SCL high is a stop condition. After a read or write sequence, the stop command places the DS3904/DS3905 into a low-power mode. See the timing diagrams for further details (Figures 2 and 3).
Variable Resistor Memory Organization
The variable resistors of the DS3904/DS3905 are addressed by communicating with the registers in Table 1.
Acknowledge
All address and data bytes are transmitted through a serial protocol. The DS3904/DS3905 pull the SDA line low during the ninth clock pulse to acknowledge that they have received each byte.
Using the Resistor as a Switch
By taking advantage of the high-impedance mode, a switch can be created to produce a digital output. Setting a resistor register to 00h creates the low state. Writing 80h into the same resistor register enables the high-impedance state. When used with an external pullup resistor, such as a 4.7k pullup, a high state is generated.
Standby Mode
The DS3904/DS3905 feature a low-power mode that is automatically enabled after power-on, after a stop command, and after the completion of all internal operations.
_____________________________________________________________________
7
Triple 128-Position Nonvolatile Digital Variable Resistor/Switch DS3904/DS3905
VCC EEPROM VCC
DS3905
RHIZ CONTROL
H0
F8h MSB GND
RESISTOR 0 7 LSB
RES 0 20k
RHIZ CONTROL SCL SDA A0 A1 A2 2-WIRE INTERFACE
H1
DATA
F9h MSB
RESISTOR 1 7 LSB
RES 1 20k
where the data is to be written. After the byte has been received, the DS3904/DS3905 transmit a zero for one clock cycle to acknowledge that the memory address has been received. The master must then transmit an 8bit data word to be written into this memory address. The DS3904/DS3905 again transmit a zero for one clock cycle to acknowledge the receipt of the data byte. At this point, the master must terminate the write operation with a stop condition. The DS3904/DS3905 then enter an internally timed write process tw to the EEPROM memory. All inputs are disabled during this write cycle.
(DS3905 ONLY)
Acknowledge Polling
H2
RHIZ CONTROL
FAh MSB
RESISTOR 2 7 LSB
RES 2 20k
Once a EEPROM write is initiated, the part will not acknowledge until the cycle is complete. Another option is to wait the maximum write cycle delay before initiating another write cycle.
Read Operations
Figure 1. DS3904/DS3905 Block Diagram
Bus Reset
After any interruption in protocol, power loss, or system reset, the following steps reset the DS3904/DS3905: 1) Clock up to nine cycles. 2) 3) Look for SDA high in each cycle while SCL is high. Create a start condition while SDA is high.
Device Addressing
The DS3904/DS3905 must receive an 8-bit device address byte following a start condition to enable a specific device for a read or write operation. The address byte is clocked into the DS3904/DS3905 MSB to LSB. For the DS3904, the address byte consists of 101000 binary followed by A0 then the R/W bit. If the R/W bit is high, a read operation is initiated. For the DS3905, the address byte consists of 1010 binary followed by A2, A1, A0 then the R/W bit. If the R/W bit is low, a write operation is initiated. For a device to become active, the value of the address bits must be the same as the hard-wired address pins on the DS3904/DS3905. Upon a match of written and hardwired addresses, the DS3904/DS3905 output a zero for one clock cycle as an acknowledge. If the address does not match, the DS3904/DS3905 return to a lowpower mode.
After receiving a matching address byte with the R/W bit set high, the device goes into the read mode of operation. A read requires a dummy byte write sequence to load in the register address. Once the device address and data address bytes are clocked in by the master, and acknowledged by the DS3904/ DS3905, the master must generate another start condition (repeated start). The master now initiates a read by sending the device address with the R/W bit set high. The DS3904/DS3905 acknowledge the device address and serially clock out the data byte. The master responds with a NACK and generates a stop condition afterwards. See Figures 4 and 5 for command and data byte structures as well as read and write examples.
2-Wire Serial Port Operation
The 2-wire serial port interface supports a bidirectional data transmission protocol with device addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are slaves. The bus must be controlled by a master device that generates the SCL, controls the bus access, and generates the start and stop conditions. The DS3904/DS3905 operate as slaves on the 2-wire bus. Connections to the bus are made through SCL and open-drain SDA lines. The following I/O terminals control the 2-wire serial port: SDA, SCL, and A0. The DS3905 uses two additional address pins A1 and A2 to control the 2-wire serial port. Timing diagrams for the 2-wire serial port can be found in Figures 2 and 3. Timing information for the 2-wire serial port is provided in the AC Electrical Characteristics table for 2-wire serial communications.
Write Operations
After receiving a matching device address byte with the R/W bit set low, the device goes into the write mode of operation. The master must transmit an 8-bit EEPROM memory address to the device to define the address
8
______________________________________________________________________
Triple 128-Position Nonvolatile Digital Variable Resistor/Switch DS3904/DS3905
SDA
MSB SLAVE ADDRESS R/W DIRECTION BIT ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SCL 1 START CONDITION 2 6 7 8 9 ACK REPEATED IF MORE BYTES ARE TRANSFERRED 1 2 3-7 8 9 ACK STOP CONDITION OR REPEATED START CONDITION ACKNOWLEDGEMENT SIGNAL FROM RECEIVER
Figure 2. 2-Wire Data Transfer Protocol
SDA
tBUF tLOW tR tF
tHD:STA
tSP
SCL tHD:STA STOP START tHD:DAT tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO
Figure 3. 2-Wire AC Characteristics
The following bus protocol has been defined: Data transfer can be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high are interpreted as control signals. Accordingly, the following bus conditions have been defined:
Bus Not Busy: Both data and clock lines remain high. Start Data Transfer: A change in the state of the data line from high to low while the clock is high defines a start condition. Stop Data Transfer: A change in the state of the data line from low to high while the clock line is high defines the stop condition. Data Valid: The state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line can be changed during the low period of the clock signal. There is
9
_____________________________________________________________________
Triple 128-Position Nonvolatile Digital Variable Resistor/Switch
COMMAND BYTE MSB START 1 0 1 0 LSB A2* A1* A0 R/W MSB DATA BYTE LSB
DEVICE IDENTIFIER SLAVE OR ADDRESS "FAMILY CODE"
RHIZ CONTROL BIT
RESISTOR SETTING
*DS3904, USE 0's INSTEAD OF A2 AND A1 FOR THE DEVICE ADDRESS
Figure 4. Command and Data Byte Structures
one clock pulse per bit of data. Figures 2 and 3 detail how data transfer is accomplished on the 2wire bus. Depending upon the state of the R/W bit, two types of data transfer are possible. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between start and stop conditions is not limited and is determined by the master device. The information is transferred bytewise and each receiver acknowledges with a ninth bit. Within the bus specifications, a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate) are defined. The DS3904/DS3905 work in both modes. Acknowledge: Each receiving device, when addressed, generates an acknowledge after the byte has been received. The master device must generate an extra clock pulse that is associated with this acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable low during the high period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the stop condition. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the command/control byte. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the command/control byte) to the slave. The slave then returns an acknowledge bit. Next follows the data byte transmitted by the slave to the master. The master returns NACK followed by a stop. The master device generates all serial clock pulses and the start and stop conditions. A transfer is ended with a stop condition or with a repeated start condition. Since a repeated start condition is also the beginning of the next serial transfer, the bus is not released.
DS3904/DS3905
EXAMPLE 2-WIRE TRANSACTIONS MSB WRITE RESISTOR 0 TO MIN POSITION START 1 0 1 0 A0h 0 0 0 LSB 0 FROM SLAVE ACK MSB 1 1 1 1 F8h 1 0 0 LSB 0 FROM SLAVE ACK MSB 0 0 0 0 00h 0 0 0 LSB 0 FROM SLAVE ACK STOP
MSB SET RESISTOR 1 TO Hi-Z START 1 0 1 0
A0h 0 0 0
LSB 0 ACK
MSB 1 1 1 1
F9h 1 0 0
LSB 1 ACK
MSB 1 0 0 0
80h 0 0 0
LSB 0 ACK STOP
MSB WRITE RESISTOR 2 TO MAX POSITION START 1 0 1 0
A0h 0 0 0
LSB 0 ACK
MSB 1 1 1 1
FAh 1 0 1
LSB 0 ACK
MSB 0 1 1 1
7Fh 1 1 1
LSB 1 ACK STOP
MSB READ RESISTOR 1 VALUE START 1 MSB 1 A0 = GND FOR DS3904 A0, A1, A2 = GND FOR DS3905 0 1 0 0 1 0
A0h 0 A1h 0 0 0 0 0
LSB 0 LSB 1 ACK ACK
MSB 1 MSB 1 1 1
F9h 1 0 0
LSB 1 LSB ACK MASTER NACK STOP REPEATED START
RESISTOR DATA
Figure 5. Example 2-Wire Transactions
10
_____________________________________________________________________
Triple 128-Position Nonvolatile Digital Variable Resistor/Switch
The DS3904/DS3905 can operate in the following three modes: 1) Slave Receiver Mode: Serial data and clock are received through SDA and SCL, respectively. After each byte is received, an acknowledge bit is transmitted. Start and stop conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after the slave (device) address and direction bit has been received. Slave Transmitter Mode: The first byte is received and handled as in the slave receiver mode. However, in this mode the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS3904/DS3905 while the serial clock is input on SCL. Start and stop conditions are recognized as the beginning and end of a serial transfer. Slave Address: The command/control byte is the first byte received following the start condition from the master device. The command/control byte consists of a 4-bit device identifier. For the DS3904, the identifier is followed by the device-select bits 0, 0, and A0. For the DS3905, the identifier is followed by the device-select bits A2, A1, A0. The device identifier is used by the master device to select which device is to be accessed. When reading or writing the DS3904/DS3905, the device-select bits must match the device-select pin(s). The last bit of the command/control byte (R/W) defines the operation to be performed. When set to a `1', a read operation is selected, and when set to a `0', a write operation is selected.
Applications Information
Power-Supply Decoupling
To achieve the best results when using the DS3904/ DS3905, decouple the power supply with a 0.01F or 0.1F capacitor. Use a high-quality ceramic surfacemount capacitor. Surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications.
DS3904/DS3905
2)
High Resistor Terminal Voltage
It is possible to have a voltage on the resistor-high terminals that is higher than the voltage connected to VCC. For instance, connecting VCC to 3.0V while one or more of the resistor high terminals are connected to 5.0V allows a 3V system to control a 5V system. The 5.5V maximum still applies to the limit on the resistor high terminals regardless of the voltage present on VCC.
3)
Chip Information
TRANSISTOR COUNT: DS3904: 6905 DS3905: 6921 SUBSTRATE CONNECTED TO GROUND
Package Information
For the latest package outline information, go to www.maxim-ic. com/packages.
Following the start condition, the DS3904/DS3905 monitor the SDA bus checking the device-type identifier being transmitted. Upon receiving the control code, the appropriate device address bit, and the read/write bit, the slave device outputs an acknowledge signal on the SDA line.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

▲Up To Search▲

Price & Availability of DS3905

	To Download DS3905 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .